A Phase-Locked Loop (PLL) is a closed-loop control circuit that produces an output signal which bears a relation to the frequency and phase of an input signal. The input signal is often considered a reference signal. A PLL can be of digital (DPLL) or analog (APLL) design. Each design has somewhat different structure, but both perform the same function. The reference signal is typically called an input clock signal (INCLK). Often, it is necessary for the PLL to take an action when the INCLK is lost. A conventional circuit for detecting the loss of an input clock is shown in diagram form in FIG. 1. In this circuit, the voltage at node F (Vf) is compared in the COMPARATOR circuit to determine if Vf bears a predetermined relationship with either a pre-designated voltage or a threshold voltage determined from the Vdd voltage of an inverter that can be incorporated within the COMPARATOR circuit. If the comparison between Vf and the pre-designated voltage or the threshold voltage falls outside of a particular tolerance, then the NOCLK output is triggered to signal that the INCLK has been lost. Circuits like those shown in FIG. 1 are problematic in determining the loss of INCLK because they are analog and Vf is dependent on factors such as the value of resistor R, the value of capacitor C, the combined resistive/capacitive (RC) effect, the delay td circuit, the NAND gate A, the circuit's Vdd voltage, and temperature. It is desirable to provide a digital circuit that is capable of detecting the loss of the INCLK of a PLL that does not rely on voltage references that are influenced by factors prevalent in analog circuits such as shown in FIG. 1.